Side Channel Analysis - A Demonstrative Approach on a 128-Bit AES Algorithm

In the recent years, with the advent of mass globalization, circuits that are being manufactured are not done end to end in the same roof. Some parts are manufactured by a company while others are being outsourced to others, sometimes even to different countries. Therefore, the security of the circuit is heavily compromised for quality and speed, thus forsaking the integrity. This is the reason why logic-locking was proposed and many methods and algorithms were tested and deployed to maintain the integrity of the circuit when it passes through IC integrator, foundry, assembly/test facilities, distributor before it reaches the end customer. While many of them have been successful, more and more attackers are finding a way to make them obsolete. One of the recent methods is by side channel analysis. This method is analysed and dealt with deeply. In this paper we demonstrate the design and implementation of a 128-bit Advanced Encryption Standard (AES) encryption algorithm and how an efficient side channel attack mollifies the strength of AES by deploying it on SASEBO-GIII FPGA board with the Xilinx Spartan and Kintex 7. The implementation has been tested successfully.