Single event transient pulse circuit cmos

The present invention provides a single event transient pulse CMOS circuit, the first buffer circuit (101), a second buffer (102), the gate PMOS transistor (103), the gate of the NMOS transistor (104) and an inverter (105) configured; wherein a first buffer for eliminating the "low high" pulse type, having an input connected to an anti-transient pulse circuit input single particle, a gate connected to the gate terminal of the output PMOS transistor (103); a second buffer for eliminating the "low level" type pulse, a transient pulse input terminal connected to an anti-particle single circuit input terminal, an output terminal connected to the gate of the NMOS transistor gate (104). PMOS transistor gate (103) with the drain of the NMOS transistor gate (104) connected to the drain, as an inverter (105) input terminal; an output terminal of the inverter (105) as a single event transient pulse circuit an output terminal.