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A 0.13m triple-Vt 9MB third level on-die cache for the Itanium 2 processor
A 0.13m triple-Vt 9MB third level on-die cache for the Itanium 2 processor
2004
Jonathan Chang
Jonathan Shoemaker
Mizan Haque
Ming Zhu Huang
Kevin Truong
Mesbah Karim
Siufu Chiu
Gloria Leong
Kiran R. Desai
Richard Goe
Sandhya Kulkarni
Asha Rao
Daniel Hannoun
Stefan Rusu
Keywords:
Parallel computing
Computer architecture
Computer science
Cache
Itanium
Explicitly parallel instruction computing
Smart Cache
Pipeline burst cache
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