Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.