Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs

A polylithic integration technology called heterogeneous interconnect stitching technology (HIST) is explored in this article. HIST provides both 2.5-D and 3-D integration capabilities enabled by multi-height and fine-pitch compressible microinterconnects (CMIs). The ANSYS Workbench simulator is used to optimize and simulate the multi-height and fine-pitch CMIs. A testbed is fabricated and assembled in order to demonstrate the key features of the proposed technology: the assembly of an anchor chip with multi-height CMIs (65 and $35~\mu \text{m}$ in height) onto a substrate with a surface-embedded chip ( $52~\mu \text{m}$ in thickness) and mechanical bonding using solder bumps. Fine-pitch CMIs ( $30\,\,\mu \text{m}\,\,\times 30\,\,\mu \text{m}$ ) are also fabricated and demonstrated in order to meet an ever-growing need for higher I/O densities for high-performance computing systems. Electrical resistance characterization results are reported as well as the mechanical characterization of interconnects.