A 10b 500MHz 55mW CMOS ADC

Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11b has faced speed limitations with a single channel [1] or employed interleaving, but with a relatively high power dissipation [2] or low SNDR [3]. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500MHz and digitize a 233MHz input with an SNDR of 53dB. This SNDR yields a figure of merit (FOM) of 0.3pJ/conversion-step, the lowest reported for 10 and 11b ADCs running at these frequencies.