Recess gate process control by using 3D SCD in 3xm vertical DRAM

As DRAM design advances from planar to vertical integration, process control of the recessed gate, generated by etching after patterning in vertical DRAM, is very critical because of the impact on device electrical characteristics and subsequent effect on yield. 3D Scatterometry Critical Dimension (3D SCD) technology is a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing. In this paper, the latest KLA-Tencor AcuShape TM modeling software with 3D SCD capability is used in the modeling and solution development, and the SpectraShape TM 8660 is used for data collection and CD measurement. Recess gate measurements were taken in the active cell area having a non-orthogonal structure. The SCD measurement results were successfully confirmed to correlate well with cross-section Scanning Electron Microscope (X-SEM) and electrical performance data.