On-line detection and compensation of transient errors in processor pipeline-structures

Based on strategies for on-line error detection in data and control path structures in simple microprocessors, this approach proposes techniques for the control- and component-error detection in high-performance processors. Detected errors are classified on-line with respect to their impact on the control and data flow. A compensation of detected errors is performed by micro rollback with different rollback distances according to pre-defined priority classes of error handling.