Reduced STI topography in metal gate transistors with large ε, by using a mask after depositing a channel semiconductor alloy

A method comprising: Forming a mask layer (204) on a first active region (202a) and a second active region (202b) of a semiconductor device (200); Forming a first etching mask in such a way (205) that this is the second active region (202b) covers and exposes the first active region (202a); Removing the mask layer (204) selectively from the first active region (202a) using the first etch mask (205); Forming a layer of a semiconductor alloy (208) on the first active region (202a) using the mask layer (204) on the second active region (202b) as a growth mask; Forming a second etch mask (210) such that it the first active region (202a) covers and the second active region (202b) leaving free, on the basis in which a lithography mask is used a lithography step, which is inverse with respect to a lithography mask for the preparation of the first etch mask (205); Removing the mask layer (204) of the second active region using the second etch mask (210); Forming a first gate electrode structure of a first transistor over the first active region (202a) and a second gate electrode structure of a second transistor over the second active region (202b), wherein the first and the second gate electrode structure of a metal-containing gate electrode material and gate insulation layer with a dielectric material having a large have e; and Forming drain and source regions in the first (202a) and second (202b) active region after formation of the first and second gate electrode structure.