Design guidelines for deep-sub-micrometer interconnections

Design guidelines for deep-submicrometer interconnections are proposed. Wiring capacitance, interconnection delays, and crosstalk noise were simulated using a three-dimensional capacitance simulator and SPICE, in order to define such interconnection parameters as the thickness and material of the conductors and insulators and the ratio of line width to spacing. Based on this analysis, it is recommended that the aspect ratio be less than one. The importance of low-resistivity metals at sub-half-micrometer dimensions is also demonstrated. The extreme limit for interconnections does not extend very far beyond 0.2 mu m, so a new design concept will be needed for deep-submicrometer VLSI circuits. >