Internal Scan Test Methodology of Sequential Circuits

Semiconductor industries goal for the quality of products is to satisfy customer requirements. Higher quantity of electronic devices can only be obtained by scan tests of the manufactured components. Scan chains are universally used in large industrial designs in order to cost effective test manufactured electronic devices. Yet, faults in the scan cells are not directly targeted by the existing tests. The main objective of this paper is to investigate the testability of the faults internal to scan cells (Sequential circuits). The major difficulty in sequential circuit testing is in determining the internal state of the circuit. Scan design techniques are directed at improving the controllability and Observability of the internal states. The approach aims to reduce the problem of testing a sequential circuit to that of testing combinational logic.