FPGA-Based Emulation of Sequential Least Squares for Coefficient Extraction of RF Power Amplifiers

The present paper shows the full design and implementation in VHDL code of the sequential least squares algorithm to obtain the coefficients of the memory polynomial model. This model was selected to perform the behavioral modeling of power amplifiers for RF. Two main parts make up the design: a memory polynomial model with unit coefficients block and a sequential least squares calculation block. The design allows the extraction of the coefficients by providing only an input and an output of the power amplifier and makes the model more accurate with each iteration, it works with complex values which makes it possible modeling the amplitude-amplitude and amplitude-phase curves in a single model. The implementation was made through the Stratix IV DSP-FPGA development board and tested using 65,536 samples from a power amplifier NXP 10W measured at 2 GHz, achieving, an NMSE of -19.6884 dB.