A study on lower saturation voltage of dual-gate thin-film a-IGZO MOS transistors

This work focuses on an amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) model with lower saturation voltage for dual-gate (DG) TFTs compared to single-gate (SG) TFTs. The addition of a backgate in dual-gate TFTs saturates the drain current at one half of the V DS required for SG devices when front and backgate oxides are matched. This behaviour can be expected for various configurations of DG TFTs. TFTs with gate and backgate shorted, with gate or back-gate connected to source, and in diode load are discussed. The derived drain current equation for DG devices explains the lower saturation voltage and allows V DS,Sat extraction. The model has been verified by characterizing different configurations, and comparing them to the device model simulations.