Variability aware interconnect timing models for double patterning
2009
A compact model for estimating delay variations due to double patterning lithography process variations on interconnect
layers is presented. Through process simulation and circuit analysis of one-dimensional interconnect topologies, the
delay response from focus, exposure, and overlay is studied. Using a process window defined by 10% linewidth change
from focus and exposure, and ±10% overlay error, a worst case change in delay of 3.9% is observed for an optimal
buffer circuit. It is shown that such delay responses can be modeled using a second order polynomial function of process
parameters. The impact of multiple interconnect variations in unique layout environments is studied using multiple
segments of interconnects each experiencing different variations. The overall delay responses are then examined, and it
is shown that for these layout structures, the separate variations combine in a manner that is both additive and
subtractive, thereby reducing the overall delay variations.
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