Set the read latency in the high-speed dram and compensation methods and apparatus

To provide a DRAM, to synchronize the read data to the read clock, and outputs at specified read latency. A by adjusting the timing of variation of the external clock signal an internal clock signal derived from, and the read clock is synchronized to be used to latch the read data and read data, the data latched in the specified read latency to ensure that arrive. From the external clock signal (116) generates a read clock (129) in the delay locked loop circuit (120), a start signal generated in response to a read command (112), the delay of the slave delay locked loop (120) through circuit (132), thereby, the same internal timing variations are introduced to the read clock signal (129) and the delayed start signal (174). With delayed start signal (174), controls the output of the read data by the read clock signal (129).