Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches

The number of marginal cells in static random-access memory (SRAM) increases as technology scales further. Spin transfer torque magnetic random-access memory (STT-MRAM) which is gaining popularity as a L3 cache alternative due to their small size, nonvolatility, high endurance, fast speed, scalability and low power consumption, also suffers from various stochastic and process variations causing both hard-errors and soft-errors in field. Orthogonal Latin Square (OLS) codes have been conventionally used in SRAMs for their low latency decoding. In this paper, an error-correcting scheme is proposed based on OLS codes which corrects both hard- errors and soft-errors simultaneously in a single step. The idea proposed is that in general a t-error correcting OLS code can be modified so that it can correct a certain number (t s < t) of soft-errors while tolerating a certain number of hard errors as well. This is achieved by storing the hard-error locations during the encoding procedure and masking the hard-error locations during the decoding procedure. A threshold voting based decoding is used instead of majority logic decoding. The proposed one-step decoding methodology is shown to have a small decoding latency. This enables high throughput for STT-MRAMs and SRAMs, even in the presence of errors, and increases their reliability. It is shown that compared to a naive increased strength code to address both hard errors and soft errors, the proposed codes achieve better hardware overhead as well as better data redundancy.