Improvement of the process overlay control for sub-40-nm DRAM
2010
In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant
progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the
development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution
limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for
developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as
complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization)
process have also applied as design rule is decreased, the improvement of process overlay control is very important.
In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual
experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with
comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the
process effects such as hard mask material, thermal process and CMP process that affect to overlay control.
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