A Design of DSP, CPU architecture on FPGA for secure routers

This paper presents the design of a DSP chip including the design of CPU architecture, instruction set, bus architecture, memory interface, and peripherals. CPU named as P10 in this article has 05 stages: Fetch, Decode, Read, Execute, Write (08 phases independent). In addition, a coprocessor (Floating Point Unit) that performs floating point 32-bit is also integrated into our design. The bus used in our work includes three protocols: APB, AHB, and AXI. Furthermore, memory M10 have up to 4GB for data space and 4MB for program space. Testing environment and secure router hardware are designed and built to verify our design on FPGA, and ASIC flow with library 65nm TSMC technology.