A 2-Channel 136-156 GHz Dual Down-Conversion I/Q Receiver with 30 dB Gain and 9.5 dB NF Using CMOS 22nm FDSOI

This paper presents a D-band 2-channel dual downconversion receiver front-end with a sliding IF architecture in 22nm FDSOI process. A fully-differential D-band low-noise amplifier (LNA) followed by an active double-balanced mixer is first used and down-converts the 137–157 GHz RF signal to an intermediate frequency (IF) of 31–40 GHz. The IF signal is split into I and Q channels and is down-converted to zero-IF output I/Q signals using a passive mixer for low 1/f noise. A x6 LO (17.5 GHz to 35 GHz and to 105 GHz) chain is included on the chip and provides the required LO for both mixers. The receiver achieves a measured peak gain of 27-30 dB, a noise figure of 9-10.5 dB at 136–154 GHz, a simulated output flicker noise corner frequency of 25 kHz and consumes 395 mW for both channels and the LO chain. The measured input P1dB is −29 dBm resulting in a high SNR for wide bandwidth signals. A measured EVM of 4.3-4.8% was achieved at 1–2 Gbaud for 16-QAM and 64-QAM waveforms. To the authors' knowledge, this work presents the first D-band CMOS I/Q receiver with application areas in dual-polarized receivers for point-to-point systems and digital beamforming MIMO arrays.