Performance of lateral SOI-MOS static induction transistors for RF power applications

Abstract Performance of lateral MOS static induction transistors on a silicon-on-insulator wafer (LSOI-MOSSIT) for RF power transistor applications has been revealed by device simulation for the first time. The feature in the device structure includes a 0.5 μm-length channel of low doping, an offset region between the gate and drain region to optimize the breakdown voltage and on-resistance, and also a body contact behind the source to suppress the floating body effect. It was found that, as the acceptor dosage in the channel decreases, the operational mode tends to change from the FET mode with saturating current–voltage characteristics to the SIT mode with non-saturating ones. It was also made clear that the channel dosage where the transition between these two modes occurs decreases with the decrease of the donor dosage of the gate-to-drain offset region. Then, both the dosage of the gate-to-drain offset region and that of the channel region were optimized to achieve a 20 V breakdown voltage and to reduce the on-resistance. The optimized structure in the SIT mode has f T of 13.2 GHz and f max of 53.1 GHz, which are superior to those of the FET mode. Finally, the simulation of Class-A amplifier has derived that the maximum power added efficiency in the SIT mode is 30.8%, which is higher than that in the FET mode by 10%.