A 286 mm2 256 Mb DRAM with x 32 Both-Ends DQ

This paper describes a 256 Mb DRAM chip archi­ tecture which provides up to x 32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 /lm CMOS technology. The chip measures 13.25 mm x 21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 0 C. In addition, a 100 MHz x32 page mode operation, namely 400 M bytefs data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated.