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A 0.68-to-1.44 GHz low-jitter all-digital phase-locked loop with a novel PFD and a high resolution DCO in 0.μm CMOS
A 0.68-to-1.44 GHz low-jitter all-digital phase-locked loop with a novel PFD and a high resolution DCO in 0.μm CMOS
2016
Xiaoying Deng
Yanyan Mo
Xin Lin
Mingcheng Zhu
Keywords:
Control engineering
Engineering
Electronic engineering
Jitter
CMOS
Phase-locked loop
low jitter
Correction
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