Novel self-stressing test structures for realistic high-frequency reliability characterization

A series of self-stressing test structures suitable for investigation of reliability failure mechanisms (hot carriers, electromigration, oxide breakdown) under realistic integrated circuit operating conditions, is described. These structures contain DC-controlled, high-frequency on-chip oscillators, which stress test structures. As a result, high-frequency (>200-MHz) stress-testing can be performed using less expensive DC test systems. In particular, hot-carrier stress-testing was performed at frequencies up to 230 MHz, which is the highest stress frequency reported for inverters. For the 1- mu m technology examined, the quasi-static model accurately describes the degradation. The statistical variation in high-frequency, hot-carrier-induced degradation is presented, and variations with temperature are shown to be consistent with DC stress results. Since only DC test systems are needed, these structures provide a simple method to calibrate reliability simulators and characterize high-frequency reliability effects. >