Performance Analysis Of Mantissa Multiplier And Dadda Tree Multiplier And Implementing With Dsp Architecture

Approximate computing provides a new approach to design high level of performance by using their technique of low-level power arithmetic circuits. Approximate computing is a technique which provides a slightly inaccurate results rather than accurate results for a scenario where an inexact result is sufficient for a purpose. Deterministic algorithm is used to view the appropriate computing techniques to overcome and attainment of efficiency. It is required to monitor different parameters from different number of systems and calculate their stability. Approximate floating-point arithmetic is used in variety of error tolerant applications such as image processing, digital processing such as filtering and Fast Fourier transform (FFT) and machine learning. The main objective of this paper is to minimize the power consumption and to rise the speed of execution by implementing an algorithm for multiplying two floating point numbers. In this paper, the existing and proposed algorithm are designed and compared in terms of area, power and delay. In order to design this, VHDL is the hardware description language used. It is simulated using Modelsim 6.3f and synthesized using Xilinx 8.1i and are further applied in Fast Fourier Transform (FFT).