Analog Performance and its Variability in Sub-10nm Fin-width FinFETs: A Detailed Analysis

This paper discusses in detail the effects of Sub-10nm fin-width ( $\text{W}_{fin}$ ) on the analog performance and variability of FinFETs. It is observed through detailed measurements that the trans-conductance degrades and output conductance improves with the reduction in fin-width. Through different analog performance metrics, it is shown that analog circuit performance, in Sub-10nm $\text{W}_{fin}$ regime, cannot be improved just by $\text{W}_{fin}$ scaling but by optimizing source/drain resistance, gate dielectric thickness together with the $\text{W}_{fin}$ scaling. We also explored the effect of process induced total and random variability on trans-conductance and output conductance of FinFETs. A systematic strategy to decouple different variability sources has been discussed and it is shown that mobility, source/drain resistance and oxide thickness are the critical parameters to reduce variability.