Low cost through silicon via solution suitable compatible with existing assembly infrastructure and suitable for single die and die stacked packages

In portable electronics products, where area is at a premium, there has been a move to three dimensional solutions, achieved by either package stacking or die stacking. Package stacking allows the parts to be tested before stacking to maintain high compound yields, but is volume and cost inefficient because each die has its own enclosure. Die stacking using wire bond interconnects is low cost, but is still volume inefficient because die must be either offset or spacer layers included to allow access to the bond pads. Die stacking using wire bonds is also incompatible with high-volume manufacture because of the serial nature of the stacking and interconnect processes. Die stacking using through silicon vias potentially offers the thinnest product solution. Despite many years of endeavour TSVs have failed to achieve widespread commercial acceptance. There are several reasons for this notable amongst which is the high capital cost of the equipment required, the slow etch rate of silicon, which curtails throughput, and the complexity of the additional process steps to fabricate conductive pipes that are insulated from the silicon through which they pass. There are also issues of reliability that have not yet been satisfactorily solved. Points of weaknesses in the design include dielectric and conductive coating of the side walls of a high aspect ratio pipe; the 90 degree bends at the top and base of the pipe that the redistribution layer must traverse and maintain connectivity during thermal cycling; and the difficulty of cleaning the back of the bond pad so the redistribution layer can make an Ohmic contact to it, when the bond pad is the bottom of a long narrow pipe. This paper will present a new through silicon via solution suitable for both single die and stacked die wafer-level packages. So-called dasiavia-through-padpsila interconnects are a novel form of interconnect that superficially resemble a TSV but the differences are important and have profound implications for the product cost and reliability. Unusually, the materials of the package construction are sourced from the automotive industry. This is done to keep costs as low as possible. The process technology is wholly scaleable so the same tool set can be used irrespective of the silicon wafer diameter. The via-through-pad interconnects and stacked package are fabricated at the wafer level to leverage the cost and throughput advantage of wafer-scale processing. Because only tested die are incorporated in the structure, high-compound yield can be realised. Data will be presented showing via-through-pad interconnects are able to surpass by a wide margin, the exacting reliability requirements of the automotive industry, both at the package and board level. Examples of application based on image sensors and muSD cards containing stacks of flash memory will be presented.