The LEADERSHIP ARCHITECT norms and validity report

An improved circuit arrangement for correcting the measured voltage of an analog speed transducer using a correction voltage derived from the speed proportional pulse train of a digital speed transducer in which the correction voltage is formed in an integrating control whose reference value is a speed proportional pulse train made up of pulses having a constant voltage-time area and whose actual value is the corrected measured voltage. The correction voltage is then added to the voltage output of the analog speed transducer in a summing amplifier to obtain the corrected measured voltage output.