A computing architecture for DFT-based band-pass filtered energy detection

This paper presents a computing architecture to implement Discrete Fourier Transform processors that measure the band-pass filtered energy at a certain component in the High-Frequency (HF) band. We achieved an analytic assessment for the HF energy detector via a scheme utilizing non-pipelined architecture at the macro-level and parallel redundant arithmetic and fully-pipelined architectures at the micro-level. This scheme was shown to improve the component utilization factor more so than using pipelined architecture at the macro-level. Performance of the scheme was analyzed with respect to the time for processing one frequency output and the number of modules required. Also, a method of the error analysis was investigated to consider the CORDIC-based DFT processor as a prospective engine for a wide range of input bit rates. >