Manufacturing and characterization of die to die interconnections for 3D applications in harsh environmental conditions

Key end user applications, such as Internet of Things (IoT), automotive, mobile internet and wearable devices, require smaller, denser and more complex packages with increased performance, all at a low power usage. Innovative front end technologies enabling transistor downscaling towards 10 nm pave the way for small pitch components with an increased I/O count, thus leading to a packaging technology revolution from simple wire bond assembly over BGA/flip chip applications towards stacked 3D-structures with through silicon vias (TSVs), micro bumps and thin dies. 3D die to wafer (D2W) stacking therefore becomes an essential and cost effective option in order to further optimize the form factor. Moreover, by stacking components onto each other instead of placing them next to each other, performance increases can be obtained due to shorter signal paths and higher possible frequencies. The work described in this paper elaborates flip chip stacking processes in combination with TSV technology for More-than-Moore (MtM) heterogeneous 3D-Wafer-Level-Chip-Scale-Package (WLCSP) integration, targeting applications in harsh environments with high demands on product reliability. The major objective comprises the proof of manufacturability at competitive costs. In addition the devices were tested against harsh automotive conditions that are present near the alternator, featuring high temperatures up to 200 °C.