UIS test of high-voltage GaN-HEMTs with p-type gate structure

Abstract This paper reports the withstanding capability of unclamped inductive switching (UIS) of high voltage GaN-HEMTs as a function of the gate voltage in the off-state. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability because of the non-removable structure of holes, which are generated by the avalanche breakdown. Therefore, a p-type GaN gate structure is attractive not only for normally-off operation but also for the UIS withstanding capability design from the viewpoint of hole-removal. This paper shows the results of the UIS test for GaN-HEMTs with the p-type gate structure. The UIS withstanding capability of GaN-HEMTs can be designed via the hole removal structure and the package thermal resistance.