A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference

We have developed a switched-capacitor CMOS voltage reference (SCVR). The circuit is shown in Fig. 24.3.2 and is composed of a low-power bias circuit [G. De Vita and G. iannacone, 2007], a core circuit and a switched-capacitor difference amplifier that is insensitive to op-amp offset voltage. The clock signals (phi 1 , phi 2 , phi 2 ') are non-overlapping to prevent leakage. The core circuit supplies V gs1 and V gs2 to the switched-capacitor difference amplifier on phases phi 1 and phi 2 , respectively. The difference amplifier then generates an output, which has a low TC, based on the gate-source voltage difference, AVGS.