Accelerating NFV application using CPU-FPGA tightly coupled architecture

Network Function Visualization (NFV) is becoming a new networking architecture for telecom carriers. NFV achieves network functions with software and commercial off the shelf (COTS) servers instead of dedicated hardware. While the software-based approach is expected to reduce costs, it could cause performance issues. CPU-FPGA tightly coupled architectures may be available in COTS servers in the near future. This paper proposes accelerating NFV application leveraging such a CPU-FPGA architecture. The proposed method of acceleration uses a data plane development kit (DPDK) ring queue, which is often used in network software, as the communication interface between the FPGA and CPU. We propose two optimizations for ring operation and table lookup operation to efficiently use the bus between FPGA and CPU. We evaluated the proposed method with an actual CPU+FPGA based platform, and an NFV application, i.e., vCPE. The results revealed that the evaluation system could accommodate 2 × 40-GbE Internet traffic, and could increase capacity as a vCPE server by x1.33.