A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in largearea time-of-ight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 m CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After xed-pattern pedestal subtraction, the uncorrected dierential non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a xed-pattern non-linearity with an RMS of