Revisiting random access scan for effective enhancement of post-silicon observability

Due to tremendous growth in complexity of modern designs, bugs inevitably escape the pre-silicon verification stage. This has led to considerable increase in the time and effort dedicated to post-silicon validation. Debugging designs at postsilicon stage faces a severe bottleneck of limited observability of the internal states. This paper presents a methodology for post-silicon debug utilizing the special features of progressive random access scan (PRAS). The PRAS offers a read-out of nondestructive scan values which is the bottleneck in the process of debugging. The proposed methodology avoids the large overhead of additional resources for debugging as the DfT architecture is reused. PRAS provides a simultaneous solution to the problems of power, data volume and application time during testing at the cost of routing overhead. The PRAS based proposed architecture offers visibility of internal states in fewer clock cycles than traditional serial scan chain based debug methods. The proposed debug scheme offers reconfigurability which enables selective visibility of internal states of a certain portion of the design. Experimental results indicate the better performance of the proposed methodology as compared to the state restoration based observability enhancement techniques.