An Active Gate Driver Design for Dynamic Voltage Balancing in Series-Connected SiC MOSFETs

With the development of silicon carbide devices, the use of low-voltage Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in series has become an option in medium/high voltage applications, but it introduces voltage imbalance problem and SiC MOSFETs suffer the great voltage peak stresses as well as the extremely high dv/dts. This brings great challenges to the insulation design of the gate driver circuit. In this study, based on the strategy of adjusting the driving signal time delay, an active gate driver is designed, it can not only reduce the design of sampling isolation through the ‘floating ground’ but also reduce the requirement for the coupling capacitance of the isolated power supply. Finally, the proposed active gate driver circuit is verified through experiments.