A 13.8pJ/conv-step Binary Search ADC with Reusable Comparator Architecture

Abstract This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only ‘N/2’ comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asyn- chronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step.