A vertex cut algorithm for model order reduction of electronic circuits

In this article we address the model order reduction problem for resistor networks by using methods from graph theory. We formulate this problem through graph theory concepts, propose algorithms for solving it, and present the computational results we have obtained for real-world resistor networks. The results demonstrate that graph-theoretical methods produce networks that contain fewer edges and are sparser than networks produced by state-of-the-art methods. Key Words: Circuit simulation, graph algorithms, model order reduction, parasitic extraction, path resistance, resistor networks, vertex cut.