Balancing method for path time delay in clock tree-type structure

The invention discloses a balancing method for path time delay in a clock tree-type structure designed from integrated circuits, which essentially comprises the following steps: (a) the path time delay values of partial inverters between root elements and each terminal element and the maximum path time delay value is defined as the target path delay value; (b) comparison of the path time delay values between each terminal element and an adjacent terminal element is made and the higher path time delay value resulting from the comparison is respectively recorded in the inverters and the root elements; (c) comparison between the path time delay value of each inverter and the target path time delay value is made; (d) a differential value between the path time delay value of each inverter and the target path time delay value is added into the path time delay value of the original inverter element; (e) the differential value is added into the recorded path time delay value of the downstream inverter of the original inverter so as to minimize the clock deviation of the clock tree-type structure.