A low-complexity 2D discrete cosine transform processor for multimedia applications

This paper describes the project of a processor for the calculation of the direct/inverse two-dimensional discrete cosine transform to be employed in videoconference applications. This processor makes use of the separability technique as calculation method and of an architecture based on distributed arithmetic, in which multipliers are replaced by accumulation-and-shift blocks. The processor was implemented on the AMS 0.8 /spl mu/m technology with semi-custom approach in order to realize an IP macro-cell to be integrated in multimedia ICs. It features a very low-complexity (15 kgates) for an overall area of 33 mm/sup 2/ and a maximum frequency of 36 MHz. Besides, the processor is fully compliant with accuracy specifications in H.263 recommendation.