Channel Optimization for the Design of High Speed I/O links
2010
The continuous increase in microprocessor performance demands an equal order of increase in the bandwidth requirements on the memory and I/O interfaces. Providing the required bandwidth at an acceptable cost is a challenge to the system packaging engineer. This paper discusseshow a passive channel can be optimized in a cost effective way to provide the maximum bandwidth. The paper focuses on the design methodology including modeling the channel, identifying the channel bottle-necks, optimizing around the bottle-necks and verifying the conclusions through simulation. Finally the simulation results are verified through hardware measurements.
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