Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting $V_{\mathrm{ MIN}}$ . Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce $V_{\mathrm{ MIN}}$ guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV $V_{\mathrm{ MIN}}$ reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.