Hole-Induced Threshold Voltage Shift Under Reverse-Bias Stress in E-Mode GaN MIS-FET

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} ) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage ( ${V}_{\text {TH}}$ ) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiN x ) gate dielectric, as SiN x does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts.