High-withstand voltage LDMOS device

The utility model relates to a high-withstand voltage LDMOS device, comprising an epitaxial layer having a first doping type and a source region and a drain region which are located on the epitaxial layer and having a second doping type. One side of the drain region, which is close to the source region, is a drift region having a second doping type and a dosage concentration lower than that of the drain region, a channel region of a first doping type is between the drift region and the source region, a gate insulating layer and a gate electrode are arranged on the channel region, a buried layer having a second doping type and a dosage concentration higher than that of the drift region is arranged under the drift region and the channel, and the buried layer is in contact with the bottom of the drift region. According to the high-withstand voltage LDMOS device in the utility model, a two-dimensional electric field is built through the buried layer arranged at the junction of the drift region and the channel region, and electric field distribution on the surface of the drift region is dispersed, thereby reducing the possibility of breakdown, and improving withstand voltage of the device.