An Optimal Design Method for Complementary Metal Oxide Semiconductor Even-Stage Ring Oscillators Containing Latches

This paper describes a design method for complementary metal oxide semiconductor (CMOS) ring oscillators composed of even-stage inverters. First, we propose a quantitative method to evaluate oscillation stability for an even-stage ring oscillator with a CMOS latch. The method uses static noise margin analysis to evaluate the static random access memory (SRAM) cell's data storage stability, by observing the similarity between the oscillator and SRAM cell circuitry. Next, the method is extended to oscillators with multiple latches. Finally, by analyzing oscillation stability using this method, we find that the range of stable oscillation conditions can be drastically widened by adding multiple single-channel latch circuits, and also by an appropriate design of their polarities and insertion positions. We also clarify through Monte Carlo simulations, that the optimized oscillator circuit is robust under process, voltage and temperature fluctuations and device characteristic variations.