The memory circuit

The invention relates to a memory circuit which comprises a plurality of sector areas, wherein each sector area at least comprises two rows of parallel storage units and a plurality of bit lines vertical to the word line; each row of storage units corresponds to one first control line, one second control line and one word line; at least two adjacent first control lines in the same section area are mutually connected, and at least two adjacent second control lines in the same sector area are mutually connected. Since at least two adjacent first control lines in one sector area are mutually connected and at least two adjacent second control lines in one sector area are mutually connected, the number of the first control lines needing to be controlled by a first control line decoding unit is reduced, and the number of the second control lines needing to be controlled by a second control line decoding unit is reduced, thereby greatly reducing the chip area occupied by the first control line decoding unit and the second control line decoding unit, and reducing the chip area occupied by the memory circuit.