Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal thin film transistor) technology. The SSTFT are used as the peripheral CMOS transistors as well as the cell transistors to save area to make the SRAM products comparative to the DRAM cell based products in the density and the cost. In the S/sup 3/ SRAM cell, the load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. Also, in a periphery, the core logic transistors are stacked on the ILD to save the layout area for maximizing cell efficiency for the products.