Respiratory Syncytial Virus Infection of Monocyte-Derived Dendritic Cells Decreases Their Capacity to Activate CD4 T Cells

An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated LI cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.