An Area Effective OFDM Transceiver System with Multi-Radix FFT/IFFT Algorithm for Wireless Applications

An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. The Pseudo-Random Binary Sequence (PRBS) will be sent as input to OFDM Transmitter, which is passed on using orthogonal frequency. Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) processors employ a significant role in OFDM transceiver design, which increases the area and power in the silicon area. The Multi-radix algorithms like Radix-22, Radix$- 2^{3}$, Radix-24 are used in the FFT/IFFT processors to decrease computational complexity. The FFT/IFFT algorithms use Urdhva Tiryakbhyam Vedic multipliers to decrease the undesired multiplication steps. To increase the speed of the multiplier, compressor adders will be introduced which reduces carry delay. The Vedic multiplier-based Multi-radix FFT/IFFT algorithms save hardware area in a silicon chip. The proposed OFDM transceiver design is implemented using Virtex-2 XC2V500-6 fg256 Field Programmable Gate Array (FPGA) device has achieved 41974-input Lookup Tables (LUTs), 2217 slices. It is operated with a maximum clock frequency of 155.35 MHz. The Multi-radix FFT/IFFT-based OFDM transceiver design reduces 84.4% slices, 68.1% 4-input LUTs and it occupies 62. 3K gates. The multi-carrier modulation technique used in the OFDM transceiver design enhances high-speed data transmission in wireless communication.