Применение структурной избыточности для повышения надежности арифметического узла вычислительного элемента бимодульной арифметики

In this work a study of hardware methods for improving reliability characteristics of arithmetic unit of computing element implemented basing on bimodular arithmetic was carried out. RNS computing element is a minimal computing unit included in RNS processor which is structured as а latticed multilayer network. Advantage of such a structural solution is the elimination of redundant hardware needed to perform non-RNS operations and their parallel execution on computing elements, and also usage of errorand fault-tolerant calculations not only for RNS operations, but for non-RNS operations as well. Choice of bimodular arithmetic as the basis for CE construction was preferred due to more economic construction of its main units regarding hardware expenditures. The most well-known types of control were considered: modulo control, hardware duplication, triplicated redundancy with majority elements. For experiments special scripts were developed, generating Verilog descriptions of arithmetic unit together with the control circuits under consideration, the results were compared with respect to additional control hardware area and the loss in performance relative to unprotected circuits.