ALLADIN: a CMOS gate matrix layout system

The proposed branch-based gate-matrix layout system provides several advantages for the automatic generation of layout under topological and speed constraints. It is, to the authors' knowledge, the simplest way to perform this automatic generation, both because it works at the symbolic level and because the basic elements which are placed, interconnected, and sized are branches, and not individual transistors. The poor cell density is largely compensated by the abutment of the cells; module density is much better than for the standard cell technique. An MOS digital filter data path designed with ALADDIN is shown. >